Symmetrical power transistor



Jan. 19, 1965 c. w. MUELLER 3,166,694

SYMMETRICAL. POWER TRANSISTOR Original Filed Feb. 14, 1958 I 2Sheets-Shee 1 for two reasons.

' the base region.

United States Patent 3,165,694 SYMMETRICAL PGWER Charles W. Mueller,Princeton, N..i., assignor to Radio Corporation of America, acorporation of Delaware ()riginal application Feb. 14, 958, Sea. N o.715,393, now

Patent No. 2,967,344. .Bivided and this application Apr. 6, 19st), Ser.No. 20,313

5 Elaims. (til. 317-235) This application is a division of applicationSerial No. 715,393, filed February 14, 1958, now US. Patent 2,967,344.

This invention relates to semiconductor devices, and more particularly,to improved devices containing a broad-area rectifying barrier, and tomethods of making such devices.

Broad-area semiconductor devices are distinguished from narrow orlimited area devices which have point contact or line contact rectifyingjunctions. Devices which contain a broad-area rectifying barrier or PNjunction may include grown junctions, didused junctions, and surfacealloyed or fused junctions. One of the most useful broad-area devices isthe junction transistor, which comprises a body of monocrystalli-nesemiconductive material including a zone or region of given conductivitytype that separates two adjacent spaced regions of opposite conductivitytype. In such units, oneof the two spaced regions is generallydenominated the emitter, while the other spaced region is known as thecollector. The in termediate zone of given conductivity type is calledthe base region.

Thin base regions are desirable in junction transistors Transistoraction depends on the injection of minority charge carriers from theemitter into The injected carriers travel by diffusion through the baseregion to the collector region. Since the diffusion of the injectedminority carriers through the base is relatively slow, the transit timeof the minority carriers through the base is one of the factors whichlimits the high frequency response of a transistor. Hence a thin baseregion is desirable to improve the electrical characteristics of thedevices at high frequencies.

Thin base regions are also desirable since some of the minoritycarriers, during their transit through the base region, recombine withthe majority carriers of the base. The thicker the base and the longerthe transit time, the more minority carriers are thus lost byrecombination. Thin base regions serve to reduce the fraction of theinjected carriers lost by recombination, and hence improve theefficiency of the device.

Although thin base regions improve the efiiciency and the high frequencyresponse of junction transistors, they have certain disadvantages. Forexample, the electrical connections to thin base regions are difiicultto fabricate, and tend to be fragile. More important, the resistance ofthe base zone of a semiconductor wafer increases as the thickness of thezone decreases. The high resistance of thin base zones limits theability of the zone to conduct high currents. If the base region is madethicker to increase the power-handling capacity of the device, theefiiciency and high frequency performance of the device is reduced. Ithas therefore been extremely difficult to design and fabricate efiicientjunction transistors which can handle sufiicient power at highfrequencies for such applications as the deflection circuits oftelevision receivers.

An object of this invention is to provide an improved method of makingimproved semiconductor devices.

Another object of the invention is to provide an improved method ofmaking broad-area junction transsistors.

Still another object of this invention is to provide improved highfrequency transistors.

3,16%,bd4i Fatentecl Jan. 19, 1965 But another object of the inventionis to provide improved symmetrical power transistors.

These and other objects are accomplished by forming a recess in onemajor face of a monocrystalline semiconductor wafer of givenconductivity type, then diffusing an opposite conductivity type impurityinto the entire wafer surface to form a surface layer over the water ofsaid opposite conductivity type. The surface layer is next removedexcept for the portion in the recess and a portion on the other majorface which is coaxially opposite the recess. The portion opposite therecess is thereby raised over the remainder of the other major waferface. To complete the device, an emitter lead is ohmically connected tothe bottom of the recess, a base tab is attached to the wafer face'whichcontains the recess, and a collector lead is attached to the oppositetype portion of the other major wafer face.

The invention will be described in greater detail by reference to theaccompanying drawing, in which:

FIGURES lA-lG are cross-sectional elevational views of successive stepsin the fabrication of a device made in accordance with one embodiment ofthe present invention;

FIGURES ZA-ZC are cross-sectional elevational views of successive stepsin the fabrication of a device made in accordance with anotherembodiment of the present invention;

FIGURES 3A-3C illustrate successive steps in the fabrication of a devicemade in accordance with another embodiment of the instant invention,FIGURE 3A being a schematic view while FIGURES 3B and 3C arecrosssectional elevational views.

A preferred example of a method in accordance with the present inventionwill illustrate the preparation of a broad-area germanium junctiontriode of the NPN type. However, it is to be understood that the methodis equally applicable in making PNP devices, and that othersemiconductors such as silicon and silicon-germanium alloys may beutilized instead of germanium.

Example I Referring to FIGURE 1A, a water of monocrystallineP-conductivity type germanium is prepared. The exact dimensions are notcritical. In this example, the wafer is 250 mils square and 8 milsthick. The wafer 10 may contain any of the conventional acceptors forthe particular semiconductor utilized. When the wafer consists ofgermanium or silicon or germaniumeilicon alloys, acceptor impuritymaterials such as boron, aluminum, gallium or indium may be employed. Inthis example, the wafer 10 contains sufficient acceptor impurities tohave a resistivity of about 4 to 6 ohm centimeters.

Referring to FIGURE 113, a mask 11 is centered on one major face of thewafer 10. The material of the mask is not critical. The shape of themask can be any desired configuration. The mask 11 may for example be anickel disc about 130 mils in diameter. The water It) is then sprayedwith an acid-resistant lacquer such as nitrocellulose, so that the wafer10 is covered with a coating 12 of the lacquer except for the portion ofthe wafer surface which was covered by the mask 11.

Referring to FIGURE 10, the mask 11 is removed and the wafer 19 isetched with an acid etchant. Preferably a slow acting etchant is used.In this example, a suitable etchant has the composition 10 partssolution A to 1 part solution B, where solution A is a mixture of 1 partconcentrated hydrofluoric acid, 3 parts concentrated acetic acid, and 6parts concentrated nitric acid, while solution B consists of .055 gramiodine dissolved in cc. of water. The etchant will attack only thatportion, of the wafer surface which was previously covered by the nickeldisc 11. A recess or well 13 is thus formed in the one major Wafer face.The shape of the recess 13 corresponds to the shape of the mask 11. Thedepth of the well 13 is readily controlled by controlling the period'oftime that the wafer is im mersed in the etchant. in this example,etching is continued until the germanium at the bottom of the well is3.2 mils thick. The wafer is then removed, Washed in deionized water toremove any remaining acid, and then washed in a solvent such as methanolor benzene to remove the lacquer coating 12.

Referring to FTGURE ID, a donor impurity, for example arsenic, isdiffused into the water. The diffusion step may be performed, forexample, by inserting the water in a quartz tube, evacuating the tube,then introducing vapors of a donor material such as phosphorus orarsenic. Other methods of accomplishing the diffusion step are describedin my copending application No. 598,180, filed July 16, 1956, and mycopending application No. 667,916, filed June 25, 1957. The wafer region14 adjacent to the surface is thereby converted to N-conductivity type.The boundary 15 between the diffused N-type region 14 and the P-tpe bulkof the Wafer 10 forms the site of a rectifying barrier or PN junction.Preferably a sufiicient amount of donor material is diffused into thewafer 10 so as to make the surface layer 1% strongly N-type. In thisexample, sufficient arsenic was diifused into the water so that theconcentration of arsenic atoms at the Wafer surface was about 10 percubic centimeter.

Referring to FIGURE 1E, a mask 16 containing a central aperture 24 isplaced over the major wafer face which includes well 13. The aperture 24in the mask 16 corresponds in size and shape to the well 13. A similarmask 17 is placed on the other major wafer face. A wax 18 is thensprayed over the unmasked portions of each r ajor wafer face. Anyacid-resistant wax may be utilized. In

A suitable etchant has the composition previously described. The waferis then washed in deionized water to remove all traces of the etchant,and is then immersed in an organic solvent such as methanol or benzeneto remove the wax. As a result of this treatment the wafer now has anN-type layer 14 at the bottom of the recess 13, and a similar N-typelayer 14 on a raised portion or boss on the opposite Wafer surfacecoaxial with the recess 13.

Referring to FIGURE 16, a metal stud 211 of about 110 mils diameter issoldered to the bottom of the recess 13. A 99 lead1 arsenic solder maybe used for this purpose. A similar metal stud 21 is attached to thecoaxially opposite N-type boss. The stud may for example be made ofsilver, or of an alloy of 99 lead-1 arsenic. The studs 20 and 21 serveto remove the heat dissipated during the operation of the device at highpower levels. The stud 26 which was soldered to the bottom of the well13 serves as the emitter connection. The stud 21 serves as the collectorconnection. Since most of the heat dissipated by a transistor isgenerated at the collector, it is advantageous to attach the studaccording to the invention can control high currents in eitherdirection. Furthermore, the base region is thin enough between thejunctions to give efficient performance at high frequencies, but isthick enough next to the base tab 19 to give a sturdy low-resistancecontact.

A modification of the embodiment described in Example I'will now bedescribed.

Example II Referring to FIGURE'ZA, a germanium Wafer is prepared asdescribed above in connection with FIGURES 1A to 1D. A metal plate 25 issoldered to the N-type' layer 14 at the bottom of the recess 13. Asimilar metal plate 26 is soldered to the opposite wafer surface coaxialwith plate 25. The plates may for example be made of an inert metal suchas silver, or of an alloy such as 99 lead1 arsenic which will notdisturb the N-type characteristics of the surface layer 14. A 99 lead-1arsenic solder may be used to make the connection. 1

Referring to FIGURE 2B, the water 1% is then treated in an acid etchantfor a sufiicient time to remove the N- type waier layer 14- from theexposed portions of the wafer. This makes the wafer 15) thinner, andleaves plate 26 resting on top of a raised pedestal or boss coaxiallyopposite the well or recess 13. The portions of the wafer beneath plates25 and 26 are not reached by the etchant and hence remain Ntype. Theunit is then washed in deionized water to remove all traces of the acid.

Referring to FIGURE 2C, an emitter lead 27 is soldered to plate 25.Plate 26 serves as the collector, and may be soldered directly to a heatsink 28 at the bottom of an encapsulating can. The heat sink 28 may forexample be a block of oxygen-free high-conductivity copper. Aring-shaped base tab 29 is soldered to the wafer around the well 13. Thedevice may then be mounted and encapsulated by conventional methods.

Another embodiment of the invention will now be described.

Example III Referring to FIGURE 3A, a relatively large block 30 ofP-conductivity type germanium is prepared. Uniform parallel grooves 31are cut in one major surface of the block 3d. The grooves 31 may beformed by masking those portions of the wafer surface, spraying theremainder of the wafer surface with wax, and treating the block 311 withan acid etchant as described above. Alternatively, a series of suchgrooves with regular rectangular cross-sections may be formed morerapidly by diamond grinding wheels. The block 30 may be about 8 milsthick, and the grinding wheels may be adjusted so that the grooves formd are about 4.8 mils deep.

Referring to FIGURE 33, the entire block 341 is diffused with a donorsuch as arsenio to produce a strongly N-type layer 32. A PN junction 33is formed at the boundary between the N-type layer 32 and the P-typebulk of the block 351.

Referring to F'iGURE 3C, selected portions of the surface of the block39 may be masked, the remaining surface covered with wax, and the unitagain treated in an acid etchant' so as to remove the N-type layer 32except for the portions immediately beneath each recess 31 and a coaxialportion on the opposite surface of the block. Alternatively, the sameconfiguration may be attained more rapidly by means of diamond grindingWheels. The block 31 is then diced by cutting it along the plane AA andthe perpendicular plane EB shown in FIGURE 3A. it will be appreciatedthat each unit will thus have a center cross-section as shown in FIGURE1F. Each unit may then be completed as discussed above in connectionwith FIGURE 16.

A junction transistor prepared in accordance with this inventionexhibits the following advantages. The voltage drop from emitter tocollector is reduced. A voltage drop as low as .18 volt has beenobtained with a 5 ampere current. The forward current transfer ratio isquite high at high currents. A collector current to base current ratioof 109 at amperes has been obtained. The switching time of the units isvery good, even at high currents. A switching time of less than 1microsecond has been observed with 5 ampere currents. metrical structureof transistors according to the invention enables them to control pulsesof 4 amperes in one direction and 6 amperes in the opposite direction.Thus these devices may be utilized for such applications as thedefiection circuits of television receivers. Power transistors of theprior art do not have the speed of response and current capacity in bothdirections which is required for such applications.

As mentioned above, the invention may also be utilized to fabricate PNPdeviws. It will be understood that PN? units may be made in amannersimilar to that described above by beginning with anN-conductivity type wafer. The wafer may consist of a semiconductor suchas silicon, germanium, or silicon-germanium alloy doped with a donorsuch as phosphorus, arsenic or antimony. A Well is formed in one waferface as described above, and then an acceptor impurity is diffused intothe wafer. The acceptor may for example be boron, aluminum, galiurn orindium. The process is then continued as described above.

There have thus been described improved semiconductor devices, andimproved methods of making such devices.

What is claimed is:

1. A transistor comprising a given conductivity type monocrystallinesemiconductor wafer having a recess in one major wafer face, a surfacelayer of opposite conductivity type in said recess, a raised waferportion on the opposite major wafer face, said raised portion beingconcentric with said recess and consisting of the aforesaidmonocry-stal-line semiconductive wafer a surface layer of said oppositeconductivity type on said raised portion, an emitter connection to saidopposite type layer in said recess, an annular base connection to saidone major Wafer face around said recess, and a collector connection tosaid opposite type surface layer on said raised portion.

2. A transistor comprising a P-conductivity type germanium wafer, arecess in one major face of said Wafer, an N-conductivity type surfacelayer in said recess, a raised wafer portion on the opposite major waferface, said raised portion being concentric with said recess andconsisting of the aforesaid monoerystalline semiconductive wafer, anN-conductivity type surface layer on said raised portion, an emitterconnection to said N-type layer The syrnin said recess, a baseconnection to said. one major wafer face, and a collector connection tosaid N-type surface layer on said raised portion.

3. A transistor comprising a P-conductivity type germanium Wafer, arecess in one major wafer face, an N -conductivity type surface layer insaid recess, a pedestal which is an integral part of said wafer andconsists of the aforesaid P-conductivity type germanium on the othermajor wafer face coaxially opposite said recess, an N-oonductivity typesurface layer on said pedestal, an emitter connection to said N-typesurface layer in said recess, a base connection to said one major waferface, and a collector connection to said N-type surface layer on saidpedestal.

4. A transistor comprising a P-conductivity type germanium wafer, a wellin the center of one major wafer face, an N-conductivity type surfacelayer in said well, a boss which is an integral part of said wafer andconsists of the aforesaid P-conductivity type germanium on the othermajor wafer face coaxially opposite said well, an N-conductivity typesurface layer on said boss, an emitter connection to said N-type surfacelayer in said well, an annular base connection to said one major waferface around said well, and a collector connection to said N-type surfacelayer on said boss.

5. A transistor comprising a P-conductivity type germanium wafer, a Wellin the center of one major wafer face, an N-conductivity type surfacelayer in said well, a metal plate over the bottom of said well, a bosswhich is an integral part of said Wafer and consists of the aforesaidP-conductivity type germanium only the other major wafer face coaxiallyopposite said well and having a diameter substantially equal to that ofsaid well, an N-conductivity type surface layer on said boss, a metalplate over the top of said boss, an emitter connection to said metalplate in said well, an annular base connection to said one major waferface around said well, and a collector connection to said metal plate onsaid boss.

References (liter! in the file of this patent UNITED STATES PATENTS2,820,154 Kurshan Ian. 14, 1958 2,829,992 Gudmundsen et al Apr. 8, 19582,847,583 Lin Aug. 12, 1958 2,947,925 Maynard et al Aug. 2, 19603,639,028 Ross June 12, 1962 3,042,565 Lehovec July 3, 1962 3,087,099Lehovec Apr. 23, 1963

1. A TRANSISTOR COMPRISING A GIVEN CONDUCTIVITY TYPE MONOCRYSTALLINESEMICONDUCTOR WAFER HAVING A RECESS IN ONE MAJOR WAFER FACE, A SURFACELAYER OF OPPOSITE CONDUCTIVITY TYPE IN SAID RECESS, A RAISED WAFERPORTION ON THE OPPOSITE MAJOR WAFER FACE, SAID RAISED PORTION BEINGCONCENTRIC WITH SAID RECESS AND CONSISTING OF THE AFORESAIDMONOCRYSTALLINE SEMICONDUCTIVE WAFER A SURFACE LAYER OF SAID OPPOSITECONDUCTIVITY TYPE ON SAID RAISED PORTION, AN EMITTER CONNECTION TO SAIDOPPOSITE TYPE LAYER IN SAID RECESS, AN ANNULAR BASE CONNECTION TO SAIDONE MAJOR WAFER FACE AROUND SAID RECESS, AND A COLLECTOR CONNECTION TOSAID OPPOSITE TYPE SURFACE LAYER ON SAID RAISED PORTION.